State of the Art Computational Ternary Logic Currnent-Mode Circuits Based on CNTFET Technology

Authors

  • Mona Moradi Young Researcher and Elite Club, Roudehen Branch, Islamic Azad University, Roudehen, Tehran, Postal code: 3973188981, Iran

Keywords:

Current Mode Logic, Ternary Current Mode Comparator, Ternary Current Mode Multiplexer, Ternary Current Mode Decoder, Ternary Current Mode Exclusive OR, CNTFET.

Abstract

Computational operations are considered as a time-consuming and important operation in ALU. These circuits play major role in computational operation in processing unit. This paper presents new computational Ternary Current Mode Circuits including comparator, multiplexer, decoder, and exclusive OR by means of Carbon NanoTube Field Effect Transistors. The new designs rely on three major parts: 1) the input currents which are converted to voltage; 2) threshold detectors; and 3) the output current flow paths to generate the outputs. The designs have been simulated based on 32nm CNFTET using Synopsys Hspice simulator.

References

E. Dubrova, “Multiple-valued logic in VLSI: Challenges and opportunities,” Proceedings of NORCHIP, pp. 340-350, 1999.

K.C. Smith, “The prospects for multivalued logic: A technology and applications view,” IEEE Transactions on Computers, vol. C-30, pp. 619-634, Sep. 1981.

D. M. Miller and M. A. Thornton, "Multiple valued logic: Concepts and representations," Synthesis lectures on digital circuits and systems, vol. 2, pp. 1-127, 2007.

E. Ozer, R. Sendag, and D. Gregg, “Multiple-valued logic buses for reducing bus energy in low-power systems,” IEE Proceedings of Computers and Digital Techniques, vol. 153, pp. 270-282, Jul. 2006.

K. C. Smith, "A multiple valued logic: a tutorial and appreciation," Computer, pp. 17-27, 1988.

S.L. Hurst, “Multiple-valued logic: Its status and its future, ” IEEE Transactions on Computers, vol. C-33, pp. 1160-1179, Dec. 1984.

K. W. Current, "Current-mode CMOS multiple-valued logic circuits," Solid-State Circuits, IEEE Journal of, vol. 29, pp. 95-107, 1994.

S. Kaeriyama, T. A. Hanyu, and M. Kameyama, "Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic," in Multiple-Valued Logic, 2000.(ISMVL 2000) Proceedings. 30th IEEE International Symposium on, 2000, pp. 438-443.

A. Kazeminejad, K. Navi, and D. Etiemble, “CML current mode full adders for 2.5-V power supply,” Proceedings of 24th International Symposium on Multiple-Valued Logic, pp. 10-14, 1994.

Y. Delican, and T. Yildirim, “High performance 8-Bit mux based multiplier design using MOS current mode logic,” 7th International Conference on Electrical and Electronics Engineering, pp. 89-93, 2011.

T. Temel, and A. Morgul, “Multi-valued logic function implementation with novel current-mode logic gates,” IEEE International Symposium on Circuits and Systems, pp. 881-884, 2002.

M. Moradi, R. Faghih Mirzaee, and K. Navi, “New current-mode Integrated ternary Min/Max circuits without constant independent current-sources,” Journal of Electrical and Computer Engineering, vol. 2015, article ID 782089, pp. 1-11, Mar. 2015.

K. Navi, M. H. Moaiyeri, and A. Momeni, "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology," Nano-Micro Letters, vol. 2, pp. 114-120, 2010.

J. Deng and H. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region," Electron Devices, IEEE Transactions on, vol. 54, pp. 3186-3194, 2007.

J. Deng and H. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking," Electron Devices, IEEE Transactions on, vol. 54, pp. 3195-3205, 2007.

Stanford University CNTFET Model website,http://nano.stanford.edu/model.php?id=23

K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B.J. Vartanian, and J.S. Harris, “Room temperature operation of a single electron transistor made by the scanning tunneling microscope nanooxidation process for the TiOx/Ti system,” Applied Physics Letters, vol. 68, pp.34-36, Jan. 1996.

C.S. Lent, P.D. Tougaw, W. Porod, and G.H. Bernstein, “Quantum cellular automata,” Nanotechnology, vol. 4, pp. 49-57, Jan. 1993.

M. Moradi, R. F. mirzaei, and K. Navi, "New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters," IEICE Transactions on Electronics, vol. 99, pp. 100-107, 2016.

R. F. Mirzaee, M. H. Moaiyeri, M. Maleknejad, K. Navi, and O. Hashemipour, "Dramatically low-transistor-count high-speed ternary adders," in Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on, 2013, pp. 170-175.

R. F. Mirzaee, K. Navi, and N. Bagherzadeh, "High-efficient circuits for ternary addition," VLSI Design, vol. 2014, p. 10, 2014.

Downloads

Published

2016-05-05

How to Cite

Moradi, M. (2016). State of the Art Computational Ternary Logic Currnent-Mode Circuits Based on CNTFET Technology. International Journal of Computer (IJC), 21(1), 50–63. Retrieved from https://www.ijcjournal.org/index.php/InternationalJournalOfComputer/article/view/610

Issue

Section

Articles