Performance Analysis and Verification of Multipliers

  • Aashu Ghalyan Samalkha Group of Institute,Kurukshetra University,Kurukshetra
  • Virender Kadyan
Keywords: Xilinx tool, power, time delay, area.

Abstract

Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. The number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation, alternative solutions at each level of abstraction are used.

At the algorithm and architecture level, this paper addresses Low-Power, High Speed and Less Area multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics.  For internal efforts, we consider recoding optimization for partial product generation, operand representation optimization, and structure optimization of partial product reduction. For external efforts, we consider signal gating to deactivate portions of a full-precision multiplier.  Several multiplier types are studied:  array multipliers, wallace multipliers, booth multiplier. In accordance to that we specify that the comparison and verification of the multiplier on basics of time delay, power and area.

 

Author Biography

Aashu Ghalyan, Samalkha Group of Institute,Kurukshetra University,Kurukshetra
Computer Science and Technology
Published
2014-06-20
How to Cite
Ghalyan, A., & Kadyan, V. (2014). Performance Analysis and Verification of Multipliers. International Journal of Computer (IJC), 13(1), 93-102. Retrieved from https://www.ijcjournal.org/index.php/InternationalJournalOfComputer/article/view/283
Section
Articles