Optimization of Speed using Compressors

  • Aashu Ghalyan Samalkha Group of Institute,Kurukshetra University,Kurukshetra
  • Virender Kadyan
Keywords: Compresser, Multiplier, Xilinx tool


The main objective of this Review is to provide high speed solutions for Very Large Scale Integration (VLSI) designers. Especially, we want focuses on the reduction of the time delay, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the time delay at the circuit, architectural and system level.

The high performance is obtained by using a new hierarchical structure, These adders are called compressors. These compressors make the multipliers faster as compared to the conventional design .


Author Biography

Aashu Ghalyan, Samalkha Group of Institute,Kurukshetra University,Kurukshetra
Department of Computer Science and Engineering
How to Cite
Ghalyan, A., & Kadyan, V. (2014). Optimization of Speed using Compressors. International Journal of Computer (IJC), 12(1), 33-38. Retrieved from https://www.ijcjournal.org/index.php/InternationalJournalOfComputer/article/view/247