PRASANTH VARASALA; BABULU KARAPA; KAMARAJU MADDU. Intelligent Clock Gating for FPGA-based RISC Architectures: A Novel Approach to Switching Activity and Dynamic Power Reduction. International Journal of Computer (IJC), Jordan, v. 51, n. 1, p. 79–89, 2024. Disponível em: https://www.ijcjournal.org/InternationalJournalOfComputer/article/view/2238. Acesso em: 3 oct. 2025.